There are many types of computer memory technologies that are presently used to store computer programs and data, including dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read only memory (EEPROM), etc. Some memory technologies require electrical power to maintain the stored data (i.e. volatile memory), while others do not (i.e. non-volatile memory). Memory technologies can be read only, write once only, or repeatedly read/write.
There is an increasing demand for repeatedly read/write, non-volatile memory. The primary non-volatile memory technology presently used is EEPROM, which utilizes floating gate field effect transistor devices each holding a charge on an insulated “floating gate”. Each memory cell can be electrically programmed with a “1” or a “0” by injecting or removing electrons onto or from the floating gate. However, EEPROM memory cells are getting more difficult to scale down to smaller sizes, are relatively slow to read and program, and can consume a relatively large amount of power.
Phase change memory devices have also been known for some time. These devices use materials that can be electrically switched (programmed) between different structured states that exhibit different electrical read-out properties. For example, memory devices made of a chalcogenide material are known, where the chalcogenide material is programmed between a generally amorphous state that exhibits a relatively high resistivity, and a generally crystalline state that exhibits a relatively low resistivity. The chalcogenide material is programmed by heating the material, whereby the amplitude and duration of the heating dictates whether the chalcogenide is left in an amorphous or crystallized state. The high and low resistivities represent programmed “1” and “0” values, which can be sensed by then measuring the resistivity of the chalcogenide material.
FIG. 1A illustrates a conventional memory cell employing chalcogenide phase change memory material. The memory cell includes a layer of chalcogenide 2 disposed between a pair of electrodes 4/6, and over thermal insulator material 8. One of the electrodes (in this case the lower electrode 4) has an increased resistivity making it a thermal heater that heats the chalcogenide layer 2 when an electrical current is passed through the electrodes 4/6 (and through the chalcogenide layer 2). FIG. 1A, for example, shows the chalcogenide 2 in its crystallized form in which the material is highly conductive, and provides a low resistance between electrodes 4/6. When heated by electrode 4 by an amorphousizing thermal pulse, at least a portion 10 of the chalcogenide layer 2 is amorphousized, as shown in FIG. 1B, which increases the electrical resistance of the chalcogenide material. The chalcogenide 2 can by crystallized back to its lower electrical resistance state by applying a crystallization thermal pulse. The electrical resistance of this memory cell can be read using a small electrical current that does not generate enough heat to reprogram the chalcogenide material.
Phase change memory devices have a high program speed (e.g. 200 ns), and exhibit great endurance and program retention. It is even possible to program the phase change memory material with varying degrees of amorphousization and thus varying degrees of resistivity, for selecting from three or more values to store in a single memory cell (multi-bit storage).
There is a constant need to shrink down the size of the memory cells, including reducing the volume of programmed memory material. The power needed to program such memory cells is generally proportional to the cross-sectional area and volume of the memory material being amorphousized/crystallized. Thus, reducing the size and volume of the memory material used in each cell reduces the electrical current and power consumption of the memory device. Smaller sized memory cells also means smaller memory arrays, and more space between memory cells for thermal isolation.
Phase change memory devices are typically made by forming blocks of the memory material in holes etched into silicon materials. Thus, the resolution of the lithographic process used to make such holes dictates the dimensions of the memory material blocks in the memory cell. To shrink the cross-sectional area of the memory material blocks even further, it is known to form spacers inside the holes before the memory material blocks are formed. See for example U.S. Pat. No. 6,511,862, which teaches forming spacers over the heating electrode, and then filling the remaining space with a block of the memory material. While this technique reduces the width of the memory material block immediately adjacent the heating electrode, it also results in the formation of the memory material block over just part of the heating electrode, which inefficiently transfers heat to the block of memory material using only part of the electrode's upper surface. This technique also fails to reduce the overall width of the memory cell, as well as effectively reduce the depth of memory material being programmed.
Shrinking the size of phase change memory cell arrays can also produce undesirable “program disturb” affects, which results when heat generated by one phase change memory cell affects the programming of phase change memory material in an adjacent memory cell. The program temperature of chalcogenide material can be as high as approximately 350° C. Well known insulators used in most CMOS fabs (e.g. silicon oxide, silicon nitride, ILD, etc.) do not provide sufficient thermal isolation in some applications to prevent the programming of one memory cell from inadvertently affecting the resistance of phase change memory material in an adjacent memory cell.
There is a need for a method and memory cell design that increases the heating efficiency of the memory cell, increases the thermal isolation between memory cells, while reducing the size of the memory cells and the amount of memory material “programmed” by the heating process.